Electromigration-Aware Integrated Circuit Design
The book provides a comprehensive overview of electromigration and its effects on the reliability of electronic circuits. It introduces the physical process of electromigration, which gives the reader the requisite understanding and knowledge for adopting appropriate countermeasures. A comprehensive set of options is presented for modifying the present IC design methodology to prevent electromigration. Finally, the authors show how specific effects can be exploited in present and future technologies to reduce electromigration’s negative impact on circuit reliability.
1. Introduction This chapter provides an overview of the evolution of microelectronics and relates it to the contents of this book, namely electromigration issues that arise during integrated circuit (IC) design and how such issues are best avoided and managed. The increasing importance of electromigration in IC design can be understood in the context of two broad developments that we explore in this chapter. First, we show that present and future development in the semiconductor industry is moving toward ever-higher current densities. And second, we discuss how boundary values for approved operation in the IC’s interconnect, such as maximum tolerable current densities, are shrinking due to smaller structure sizes. As a consequence of these two fundamental and contradictory developments, we show how electromigration issues are becoming a crucial, and indeed in many cases critical, IC design criterion, which motivates their in-depth study in this book. The chapter concludes with an overview of the book’s more detailed content, which the reader should now be able to relate to these two broad developments.
1.1 Development of Semiconductor Technology
1.2 Interconnect Technology
1.3 The Rise of Electromigration
2. Fundamentals of Electromigration This chapter investigates in detail the actual low-level migration processes. A solid grounding in the physics of electromigration (EM) and its specific effects on the interconnect will give us the knowledge to establish effective mitigation methods during the design of integrated circuits. We first explain the physical causes of EM (Sect. 2.1) and then present options to quantify the EM process (Sect. 2.2), which enable us to effectively characterize key aspects of the process and its effects. In Sect. 2.3, we introduce EM-influencing factors arising from the specific circuit technology, the environment, and the design. We then investigate detailed EM mechanisms with regard to circuit materials, frequencies, and mechanical stresses (Sect. 2.4). Since EM is closely related to thermal and stress migration that also occur in the conductors of electronic circuits, we examine their inter-dependencies (Sect. 2.5). Finally, Sect. 2.6 outlines the principles of a migration analysis through simulation. This honors the importance of finite element modeling (using the finite element method, FEM) in electromigration analysis and enables the reader to develop and apply similar modeling and simulation techniques.
2.2 Electromigration Quantification Options
2.3 Design Parameters
2.4 Electromigration Mechanisms
2.5 Interaction of Electromigration With Thermal and Stress Migration
2.6 Migration Analysis Through Simulation
3. Integrated Circuit Design and Electromigration This chapter describes measures for modifying the present integrated circuit design methodology with the objective of countering electromigration. After introducing the overall design flow (Sect. 3.1) in use today, we explore how analog and digital designs are differentiated, as both areas require different measures to counter electromigration (Sect. 3.2). Understanding that knowledge of the currents flowing in interconnects is a fundamental requisite for an electromigration-aware design flow, we discuss in Sect. 3.3 the different types of currents encountered and show how sensible current values can be determined. Section 3.4 describes how robust current-density boundary values can be determined, using application and reliability specifications provided in mission profiles. Effective current-density verification is at the core of electromigration-aware design flows (Sect. 3.5). In Sect. 3.6, we present options for dealing with problems identified by current-density verification, using layout adjustment techniques. In the final Sect. 3.7, we put forward a number of farther-reaching measures for increasing current-density boundary values, based on our assessment of current technological trends.
3.1 Design Flow of Integrated Circuits
3.2 Electromigration-Aware Design Flows
3.3 Determination of Currents
3.4 Determination of Current-Density Limits
3.5 Current-Density Verification
3.6 Post-Verification Layout Adjustment
3.7 Design Options for Electromigration Avoidance
4. Mitigating Electromigration in Physical Design The goal of this chapter is to summarize the state of the art in EM-mitigating effects. Sections 4.2–4.7 describe in detail all known EM-inhibiting effects upon which an “electromigration awareness” is based. We also consider material-related options to reduce EM, such as surface passivation (Sect. 4.8), and the use of EM-robust materials, such as carbon nanotubes (Sect. 4.9). We determine parameters for every measure, which enable them to be used easily; we also provide detailed advice for applying each method. We show how approved current densities can thus be increased at critical points, for example, by means of local layout modifications. The presented measures provide circuit designers with a suite of options to prevent electromigration damage in present, and future, technology nodes. Ultimately, the challenge is to avoid exceeding permissible current densities by selectively increasing the permissible boundaries.
4.1 Overview of Presented Measures and Effects
4.2 Bamboo Effect
4.3 Critical Length Effects
4.4 Via-Below and Via-Above Configurations
4.6 Multiple Vias
4.7 Frequency-Dependent Effects
4.8 Materials for Classical Metal Routing
4.9 New Materials and Technologies
5. Summary and Outlook This chapter summarizes the key findings and results of the book and presents our outlook on future developments. Section 5.1 reiterates the available options and useful measures to prevent electromigration damage in current design flows; it also includes practical guidelines of their application. Sections 5.2–5.5 indicate how to facilitate an electromigration-compliant layout design in future electromigration-critical technology nodes. Here, key measures are a pattern generator to produces electromigration-robust layout elements, applying new technologies, such as carbon nanotubes (CNTs), and the evolution toward constraint-driven design methodologies.
5.1 Summary of Electromigration-Inhibiting Measures
5.2 Outlook: Segment Lengths
5.3 Outlook: Library of Electromigration-Robust Elements
5.4 Outlook: New Technologies
|Last update: 16.04.2018|