Research Focus
Design automation for interposer-based 3D ICs
Interposer-based 3D ICs—also known as 2.5D ICs—promise higher yield and better heat dissipation over classical 2D ICs. Such 3D ICs are currently commercially available in a few products, like FPGAs and GPUs, and they are viable contenders for the next-generation chip market. However, the designing of these products requires some notable manual intervention for placement, simulation, verification, etc.; available tools are still inadequate according to academia and industry experts.
To address this issue, we are developing the automated design methodologies for interposer-based 3D ICs, including approaches for die placing,
interposer routing, thermal analysis and pin assignment.
Read our overview of design challenges for interposer-based 3D ICs
Research Interests
Optimal Die Placement on the Interposer
We developed an effective method for optimal wirelength-driven die placement of interposer-based 3D ICs.
Our key ideas are to leverage the constraint-satisfaction problem (CSP) formalism in combination with a branch-and-bound (B&B) algorithm,
and to develop several novel techniques for early identification and pruning of unpromising configurations. Such pruning techniques
dramatically, yet accurately, confine the solution space and quickly rule out unpromising placements. Thus, we obtain optimal placement
solutions in significantly shorter runtime than prior art, and we can optimally handle larger problem instances than prior art.
Related publication
Downloads
Corblivar 3D-Floorplanner, zur Planung von massiv-parallelen Verbindungsstrukturen in 3D-ICs
Experimentelle Software
Corblivar, neuester Stand bei GitHub
HotSpot, neuester Stand bei GitHub
Binary of the optimal interposer placement tool (supports parallel execution):
Please consider this software experimental
Binary compiled on Ubuntu 16.04 with gcc 5.4.0 (dynamically linked)
Statically linked binary compiled on Ubuntu
Benchmarks
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