Dresden University of Technology
Institute of Electromechanical and
Electronic Design

Dr.-Ing. Johann Knechtel Former Researcher, now with New York University Abu Dhabi

German

 

Publications (English only):

• S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, S. Rakheja, "Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices," in Proc. Design Automation and Test in Europe (DATE), 2018, to appear

• S. Patnaik, J. Knechtel, M. Ashraf, O. Sinanoglu, "Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing," in Proc. Asia South Pacific Design Automation Conference (ASPDAC), 2018, to appear

• S. Osmolovskyi, J. Knechtel, I. L. Markov, J. Lienig, "Optimal Die Placement for Interposer-Based 3D ICs," in Proc. Asia South Pacific Design Automation Conference (ASPDAC), 2018 (PDF)

• J. Knechtel, J. Lienig, I. A. M. Elfadel, "Multi-Objective 3D Floorplanning with Integrated Voltage Assignment," in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 2, Article 22, 2017 (PDF)

• A. Sengupta, S. Patnaik, J. Knechtel, M. Ashraf, S. Garg, O. Sinanoglu, "Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques," in Proc. International Conference On Computer Aided Design (ICCAD), 2017 (PDF)

• S. Patnaik, M. Ashraf, J. Knechtel, O. Sinanoglu, "Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging," in Proc. International Conference On Computer Aided Design (ICCAD), 2017 (PDF)

• J. Knechtel, O. Sinanoglu, I. A. M. Elfadel, J. Lienig, C. C. N. Sze, "Large-Scale 3D Chips: Challenges and Solution for Design Automation, Testing, and Trustworthy Integration," in IPSJ Transactions on System LSI Design Methodology (TSLDM), Invited paper, Vol. 10, pp. 45-62, 2017 (PDF)

• J. Knechtel, O. Sinanoglu, "On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity," in Proc. Design Automation Conference, 2017 (PDF)

• J. Knechtel, J. Lienig, "Physical Design Automation for 3D Chip Stacks – Challenges and Solutions," in Proc. International Symposium on Physical Design, Invited paper, pp. 33-40, 2016 (PDF)

• P. Budhathoki, J. Knechtel, A. Henschel, I. A. M. Elfadel, "Integrating 3D Floorplanning and Optimization of Thermal Through-Silicon Vias," in 3D Stacked Chips – From Emerging Processes to Heterogeneous Systems, I. A. M. Elfadel, G. Fettweis (eds.), Springer, ISBN 978-3-319-20480-2, 2016 (Link)

• J. Knechtel, J. Lienig, C.C.N. Sze, "Challenges and Future Directions of 3D Physical Design," in Physical Design for 3D Integrated Circuits., A. Todri-Sanial, Ch. S. Tan (eds.), CRC Press, ISBN 978-1-498-71036-7, pp. 357-386, 2015 (Link)

• J. Knechtel, E. F. Y. Young, J. Lienig, "Planning Massive Interconnects in 3D Chips," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 11, pp. 1808-1821, 2015 (PDF)

• J. Knechtel, "Interconnect Planning for Physical Design of 3D Integrated Circuits," PhD dissertation, in Fortschritt-Berichte VDI Reihe 20 Nr. 445, VDI-Verlag Düsseldorf, ISBN 978-3-18-345520-1 ISSN 0178-9473, 2014 (link to hardcopy, citable link to softcopy)

• J. Knechtel, E. F. Y. Young, J. Lienig, "Structural Planning of 3D-IC Interconnects by Block Alignment," in Proc. Asia South Pacific Design Automation Conference, pp. 53-60, 2014 (PDF)

• P. Budhathoki, J. Knechtel, A. Henschel, I. Elfadel, "Integration of Thermal Management and Floorplanning Based on Three-Dimensional Layout Representations," in Proc. International Conference on Electronics, Circuits, and Systems, pp. 962-965, 2013 (PDF)

• R. Fischbach, J. Knechtel, J. Lienig, "Utilizing 2D and 3D Rectilinear Blocks for Efficient IP Reuse and Floorplanning of 3D-Integrated Systems," in Proc. International Symposium on Physical Design, pp. 11-16, 2013 (PDF)

• J. Knechtel, I. L. Markov, J. Lienig, M. Thiele, "Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration," in Proc. International Conference on Computer-Aided Design, pp. 705-712, 2012 (PDF)

• J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2-D Blocks into 3-D Chips," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 2, pp. 228-241, 2012 (PDF)

• R. Fischbach, J. Lienig, J. Knechtel, "Investigating Modern Layout Representations for Improved 3D Design Automation," in Proc. Great Lakes Symposium on VLSI, pp. 337-342, 2011 (PDF)

• J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2D Blocks into 3D Chips," in Proc. International Symposium on Physical Design, pp. 81-88, 2011 (PDF)

 Impressum

Last update: January 29, 2018